一种低功耗CMOS并行双频低噪声放大器  

Low power consumption CMOS concurrent dual-band low noise amplifier

作　　者：申晶[1] 张晓林[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100191

出　　处：《吉林大学学报（工学版）》2013年第2期485-490,共6页Journal of Jilin University:Engineering and Technology Edition

基　　金：国防科工委民用航天专项项目;北京市重点学科基金项目(XK100060525)

摘　　要：基于SMIC 0.18μm 1P6M CMOS工艺,设计实现了一种低功耗单端输入转差分输出的并行双频低噪声放大器。采用带有源级电感负反馈的共源共栅结构,在功耗限制下在双频段对输入阻抗和噪声性能同时进行优化,实现并行接收,并具有单端输入转差分输出的功能。该低噪声放大器核心电路尺寸为450μm×350μm。仿真表明,低噪声放大器(LNA)在1.227GHz和1.575GHz工作频率处的输入回波损耗分别为-11.61dB和-12dB,功率增益分别为14.67dB和12.68dB,噪声系数分别为2.3dB和2.53dB,输入l dB压缩点分别为-18.5dBm和-14.5dBm。在1.8V电源电压下,功耗仅为8.4mW,可用于航空航天领域的电子系统中。A concurrent dual-band low-noise amplifier （LNA） with single-ended input and differential output which was characterized by low power consumption was designed and implemented based on SMIC 0.18μm 1P6M CMOS process. Using the cascode structure with inductive source degeneration, the input resistance and noise performance were optimized simultaneously at 2 different bands under power constraint, and the concurrent receive was achieved with single-ended input and differential output. The size of the LNA core circuit is 450 μm×350 μm. The LNA consumes power.8.4 mW at a power supply voltage of 1.8 V. The simulations showed that at working frequencies 1. 227 GHz and 1. 575 GHz, its power gains were 14.67 dB and 12.68 dB, the input return losses were - 11.61 dB and -12 dB, the noise coefficients were 2.3 dB and 2.53 dB, and the input 1 dB compression points were -18. 5 dBm and -14. 5 dBm, respectively. The LNA can be used in concurrent dual-band global positioning system receiver for its good input match, low noise, and high linearity at dualband.

关 键 词：半导体技术 低噪声放大器 并行双频 导航接收机 低功耗 

分 类 号：TN432[电子电信—微电子学与固体电子学]