CDMA下行同步算法设计与FPGA实现  

Design and Implementation of CDMA Downlink Synchronization Based on FPGA

作　　者：罗森[1] 田增山[1] 周启平[1] 

机构地区：[1]重庆邮电大学 无线定位与空间测试重点实验室,重庆400065

出　　处：《电视技术》2013年第5期155-159,共5页Video Engineering

摘　　要：针对CDMA下行同步快速高效的要求,设计FFT快速相关算法,实现了FPGA快速同步。详细分析了基于FFT的下行同步算法及其参数的确定,给出实现该算法的模块图和各模块基于Verilog的程序实现,并进行了基于ModelSim的程序仿真,将其结果和MATLAB仿真结果进行对比验证。最后以FPGA Stratix Ⅱ芯片为硬件平台进行板级调试,结果表明该同步算法稳定可靠。The fast correlation algorithm based on FFY module is designed and the CDMA downlink synchronization algorithm based on FPGA is imple- mented. The downlink synchronization algorithm and the choosing of related parameters are analyzed. The module diagram of the algorithm and imple- mentation of the program based on Verilog are introduced and the procedure is simulated using ModelSim and the results are compared with the output of MATLAB to verify algorithm. Finally, the debugging on board of Stratix II is made and the results show the synchronization algorithm has a good stability.

关 键 词：CDMA 下行同步算法 FPGA 

分 类 号：TN949.6[电子电信—信号与信息处理]