面向多核结构的自适应选择性指令主动推送技术  

An Adaptive and Selective Instruction Active Push Technique for Multi-core Architecture

作　　者：张骏[1] 梅魁志[1] 赵季中[1] 

机构地区：[1]西安交通大学电子与信息工程学院,西安710049

出　　处：《小型微型计算机系统》2013年第3期636-643,共8页Journal of Chinese Computer Systems

基　　金：国家"核高基"科技重大专项课题项目(2009ZX01039-003-001-03;2009ZX01023-004)资助;国家自然科学(60905007)资助

摘　　要：正确有效的指令预取策略是避免指令缺失的关键技术,程序流程改变时指令预取方向正确率不高、指令预取准确度和存储器带宽有效利用率较低是导致指令缺失的主要因素.本文提出基于置信度评估的自适应选择性指令主动推送技术ASIAP,一方面减少无效指令预取的数量,进行精确指令预取,在避免Cache污染的同时提升指令预取的有效性;另一方面采用指令主动推送部件自适应选择性地完成部分非顺序指令预取请求,减少了取入错误路径上无用指令的可能.通过与Next_Line、Target_Line、Wrong_Path、BTA、Markov和CFGP等策略的对比,在2-16内核配置下,ASIAP策略相对于其它策略准确性平均提升3.7%-28.71%;L1 I-cache缺失率平均下降3.3%-14.39%.Correct and effective instruction prefetching strategy is key technique to avoid instruction miss.Unfortunately,correctness and accuracy of instruction prefetching is not very precise,and the utilization ratio of memory bandwidth is relative low,which lead to instruction miss.This paper proposes an adaptive and selective instruction active push technique for multi-core architecture,called ASIAP.On one hand,in order to avoid the cache pollution and increase the prefetching validity,we perform instruction prefetching precisely as far as possible;on the other hand,part of non-sequential type prefetching are responded preferentially by a specific instruction active push unit adaptively and selectively,which decreases the possibility of fetching the useless instructions in the wrong path.We evaluate ASIAP with other prefetching strategies such as Next_Line、Target_Line、Wrong_Path、BTA、Markov and CFGP.Simulation result indicates that,under the configuration of 2 cores to 16 cores,relative to other strategies,ASIAP improves prefetching accuracy by average 3.7%-28.71%,and reduces of L1 I-Cache miss rate by average 3.3%-14.39%.

关 键 词：片上多核处理器 存储系统 置信度评估 自适应 指令预取 主动推送 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]