高速ADC交叉采样控制器的FPGA实现  

FPGA Realization of High-speed ADC Time-interleaving Sampling Controller

作　　者：程耀林[1] 

机构地区：[1]中南民族大学电信学院,湖北武汉430074

出　　处：《仪表技术与传感器》2013年第1期36-38,78,共4页Instrument Technique and Sensor

基　　金：中南民族大学校基金资助项目(YZY07003)

摘　　要：设计了2通道和4通道高速ADC交叉采样控制器,可以把采样速率分别提高到2倍和4倍。对高速ADC,使用CPU无法满足速度要求,所以使用FPGA实现控制。控制器使用了FPGA片内锁相环产生具有等相位差的采样时钟、输出时钟和控制信号,对输入的ADC交叉采样数据进行交叉处理,然后输出合成的高速采样数据。仿真结果表明,这种交叉采样的控制算法是可以实现的。The high-speed ADC time-interleaving sampling controllers with 2-channel or 4-channel were designed. Its sampling rate can be increased to 2 times and 4 times respectively. The CPU can not meet the speed requirements for high-speed ADC, so the paper used FPGA to achieve control. The controller used FPGA-chip PLL to generate sampling clocks with the equal phase difference, the output clock and control signals, and cross-processed the input data from all ADC time-interleaving sampling data, and then outputted high-speed synthesis of the sampling data. The simulation results show that the control algorithm for time-interleaving sampling can be realized.

关 键 词：高速ADC 交叉采样 FPGA 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]