基于FPGA的误码仪设计与实现  

Design and realization of bit error tester based on FPGA

作　　者：陈小敏[1] 朱秋明[1] 虞湘宾[1] 孟田珍[1] 

机构地区：[1]南京航空航天大学电子信息工程学院,江苏南京210016

出　　处：《中国现代教育装备》2013年第3期4-6,共3页China Modern Educational Equipment

基　　金：南京航空航天大学教育教学改革研究项目"通信原理课程研究型教学方法的探索与实践"资助

摘　　要：误码率是评价数据传输设备及其信道工作质量的一个重要指标,而误码仪作为通信系统的可靠性测量工具,广泛用于传输设备的生产调试、检验以及日常维护维修,旨在完成一个高斯衰落信道下数字基带系统的实现及其误码率性能的测试。借助FPGA实验平台,通过Verilog语言在FPGA芯片上编程以实现数字基带信号的产生、星座映射、基带成型、信道、匹配滤波、判决、解映射、误码计算等模块,并通过FPGA的数码管显示误码率。The bit error rate is an important indicator for evaluating the data transmission equipment and its channel quality, while the bit error tester, as a tool to test the reliability of a communication system, is widely used in the production, testing, inspecting and maintenance of transmission equipment. In this paper, a bit error tester for digital baseband communication systems over Gaussian fading channel is designed, and the corresponding test of bit error rate （BER） performance can be realized. By means of FPGA experiment platform, the production of the digital baseband signals, constellation mapping, baseband shaping, channel, matched-filter, decision, de-mapping, and the calculation of BER can be realized by programming with Verilog language. Moreover, the resultant BER can be displayed with FPGA.

关 键 词：通信系统 误码仪 FPGA MATLAB 

分 类 号：TN914.3[电子电信—通信与信息系统]