An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling  

作　　者：朱晓石 陈迟晓 徐佳靓 叶凡 任俊彦 

机构地区：[1]State Key Laboratory of ASIC & System,Fudan University [2]Microelectronics Science and Technology Innovation Platform,Fudan University

出　　处：《Journal of Semiconductors》2013年第3期76-80,共5页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.61006025);the Special Research Funds for Doctoral Program of Higher Education of China(No.20100071110026)

摘　　要：A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.

关 键 词：sample-time error digital-to-skew converter bootstrapped switch calibration time-interleaved 

分 类 号：TN792[电子电信—电路与系统]