LVDS高速并口通信协议设计  

The design of high speed LVDS parallel port communication protocol

作　　者：杨雷[1] 龙哲仁[1] 卢继华[1] 孙磊[1] 

机构地区：[1]北京理工大学信息与电子学院,北京100081

出　　处：《电子技术应用》2013年第3期119-122,共4页Application of Electronic Technique

基　　金：国家高技术研究发展计划项目支持(2012AA121604)

摘　　要：提出高速数据传输系统中IEEE802.3千兆网卡与同步静态存储器间非对称点对点高速通信接口和通信协议设计方案,接口速率不低于1 Gb/s。基于高速接口中常用的低电压差分信号技术,电气连接单向使用5路低摆幅差分信号对,其中1路时钟,4路数据,双沿采样源同步传输;基于适用于短传播延时的停止等待自动重复请求协议,通信协议使用命令——应答机制;利用模256校验保证数据的可靠传输。理论分析表明,通信接口带宽可达1.2 Gb/s,协议效率在99%以上,协议工作稳定可靠,在满足千兆网卡全速接收转发数据的情况下,高速并口带宽仍有裕量。In the high speed data transmission system, a high speed dissymmetrical point to point communication port and protocol between IEEE802.3 GENIC （Gigabit Ethernet Network Interface Card） and SDRAM are designed, while the port＇s speed should not below 1 Gb/s. Port＇s electrical connection are based on LVDS （Low Voltage Differential signaling）, and five LVDS pairs are used in one direction, while one clock and four data. Double-edge sampling and source-synchronize are also used. Based on STOP-WAIT ARQ protocol, command and acknowledgment mechanism is used. Mode 256 checkout is used to guarantee the reliable data transmission. Analysis shows that the port＇s bandwidth is 1.2 Gb/s, and the efficiency of protocol is above 99%. Finally, the protocol works steadily and trustily in system. When the GENIC receive and transmit data at fully speed, the port＇s bandwidth remain nonzero.

关 键 词：高速传输系统 LVDS并口 通信协议 停止等待 IEEE802 3 

分 类 号：TN919.3[电子电信—通信与信息系统]