基于Virtex-5的DDR2内存条存储管理  

Storage Management of DDR2 Memory Bank Based on Virtex-5

作　　者：贺美华[1] 钱锐[2] 郑飞雁[1] 

机构地区：[1]中国人民解放军95486部队95分队 [2]电子科技大学电子工程学院

出　　处：《电脑编程技巧与维护》2013年第6期96-97,106,共3页Computer Programming Skills & Maintenance

摘　　要：详细介绍了在Xilinx Virtex-5系列FPGA中利用MIG2.0 IP核实现高性能的DDR2 Dual Rank内存条控制器的设计原理以及这种设计结构的独特性。针对实时数字信号处理系统需要大规模且高速的测试数据,以此平台为基础,在用户层实现了适合本应用背景的控制状态机。系统测试结果表明,该设计满足大容量存储和高速输出的要求。This article elaborates the design principle of using MIG2.0 IP core in FPGA of Xilinx Virtex-5 series to realize the controller of DDR2 Dual Rank memory bank in high performance, which also mentions the uniqueness of this design structure. Based on this peafform, this system implements the control state machine in the user layer satisfying the application background that real-time digital processing system requires a large number of test data. The system test result reveals that this design meets the requirement of mass storage and high rate output.

关 键 词：测试系统 DDR2内存条管理 Virtex-5系列 高性能方案 

分 类 号：TP333.1[自动化与计算机技术—计算机系统结构]