“类整数DCT”变换快速并行算法的硬件实现  

Hardware Implementation for Fast and Parallel Algorithm of Variety Integer DCT Transform

作　　者：刘昊[1] 吴君钦[1] 

机构地区：[1]江西理工大学信息工程学院,江西赣州341000

出　　处：《电视技术》2013年第7期33-35,153,共4页Video Engineering

摘　　要：在分析"类整数DCT"变换基生成规则及其优越综合性能的基础上,设计了一种基于硬件流水线的"类整数DCT"变换快速并行算法的硬件结构,用加法和移位操作实现整数乘法。该设计结构简单、运算速度高、易于与微处理器系统接口,类整数DCT变换及其快速硬件流水算法的获得,为进一步降低视频编解码器的复杂度,提供了一个有价值的参考方案。Analysis of the generated rules and superiority of ＂variety integer DCT transform radix＂. In this paper, a hardware structure is designed based on a hardware pipeline for the parallel algorithm of variety integer DCT transform radix, integer multiplication is implemented by using shifting and addition operation. This design has a simple structure, high speed of operation and can easily interface to the microprocessor system, the fast and parallel algorithm of variety integer DCT transform radix supplies a new valuable solution for reducing the complexity of the video coder and decoder.

关 键 词：图像编码 整数DCT 去相关 并行算法 硬件结构 

分 类 号：TN919.81[电子电信—通信与信息系统]