FPGA中CIC抽取滤波器增益校正的实现  

Realization of CIC Decimation Filter Gain Correction in Application of FPGA

作　　者：金燕[1] 李松 冯晓东[1,2] 

机构地区：[1]重庆邮电大学电信业务支撑系统研究所,重庆400065 [2]重庆会凌电子新技术有限公司,重庆400065

出　　处：《电视技术》2013年第7期57-59,共3页Video Engineering

摘　　要：在中频数字化信号处理中,FPGA应用越来越广泛,DDC的FPGA模块化非常必要,CIC滤波器由于其结构只用到加法器和延迟器,很适合用FPGA来实现,通常工作在DDC系统中运算量大的第一级。分析了CIC滤波器的抽取原理、性能、影响参数及增益产生原因,针对实际应用中5级CIC滤波器在不同抽取率下对信号进行抽取时所产生的增益问题,给出了校正方法,并在Modelsim仿真中得到了验证。In IF digital signal processing, the applications of FPGA are used more widely. DDC FPGA modular is necessary. Since its structure uses only adders and delayers, a CIC filter is achieved suitable for FPGA. CIC filters usually work in the first level with large amount of computation in DDC system. This paper first analyzes the theory, performance, impact parameters and gain generation reason of the CIC filter, for the problem that gain gen- erated when five stages CIC decimation filter works under different decimation rates in practical application, and then gives the method of gain correction. Finally, it is verified in Modelsim Simulation.

关 键 词：CIC抽取滤波器 FPGA 增益校正 

分 类 号：TN713.7[电子电信—电路与系统]