基于FPGA的并行DDS技术研究  

Research on parallel direct digital synthesis technology based on FPGA

作　　者：黄志林 

机构地区：[1]北京无线电计量测试研究所,北京100854

出　　处：《现代电子技术》2013年第7期54-56,共3页Modern Electronics Technique

摘　　要：输出频带过窄是限制直接数字频率合成（DDS）发展的瓶颈之一。提出了多路并行DDS原理并且给出了具体案例，设计实现了输出频率在400～700MHz范围内杂波抑制优于50dBc，频率分辨力小于0．5Hz，且便于后续实现各种调制。该DDS电路同时具有接口简单，使用灵活等优点，可用于在雷达、电子战领域的宽带细分辨力信号产生。Narrow output frequency band is one of the key factors to restrict DDS＇s application. This paper provided the principle of multi-channel parallel direct digital synthesis and its application, In this design, when the output signal frequency covers 400 - 700 MHz, the clutter suppression is above 50 dBc and the frequency resolution is below 0.5 Hz. It is easy to modulate anytime. The circuit has the advantages of simple interface, and flexible use, and it can be used in broadband and high frequency resolution signal production field such as radar and electronic warfare.

关 键 词：并行直接数字频率合成 宽带 杂波抑制 分辨力 

分 类 号：TN743.4[电子电信—电路与系统]