实时图像采集系统的FPGA逻辑设计与实现  

Logic Design and Realization of Real-Time Image Acquisition System Based on FPGA

作　　者：戚秀真[1] 周颖 

机构地区：[1]长安大学信息工程学院,陕西西安710064 [2]陕西邮电职业技术学院计算机系,陕西咸阳712000

出　　处：《电子科技》2013年第4期22-24,共3页Electronic Science and Technology

基　　金：中央高校基金资助项目(CHD2011JC045)

摘　　要：提出了一种实时图像采集系统的设计方案。阐述了图像采集系统中的总线形成、高速缓存和SDRAM控制器3个关键技术,并给出了FPGA控制逻辑和实现方法。该系统时钟>60 MHz,实现了多分辨率灰度和彩色图像的采集,像素时钟>30 MHz,帧频没有限制。A design scheme of real-time image acquisition system is presented in this paper. The key technolo- gy of bus generation, high-speed buffer and Synchronous Dynamic Random Access Memory （SDRAM） of the image acquisition system are expatiated. The control logic and realization of FPGA are presented. The AT system clock is more than 60MHz, and the pels clock is more than 30 MHz. The acquisition of grey and color image with high-reso- lution is realized without limit to the frame rate.

关 键 词：图像采集 高速缓存 FPGA SDRAM 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]