高性能可重构流水线ADC的设计与仿真  

Design and simulation of high-performance and reconfigurable pipelined ADC

作　　者：陈振宇[1] 王立志[1] 任晓岳[1] 

机构地区：[1]空军工程大学理学院,陕西西安710051

出　　处：《电子技术应用》2013年第4期39-41,44,共4页Application of Electronic Technique

摘　　要：提出了一种14 bit、100 MS/s可重构流水线ADC的设计方案,在采样/保持电路、栅压自举开关、折叠式共源共栅运算放大器、可重构控制器等关键电路上均有明显改进,降低了非理想因素对系统的影响,保证了所设计的流水线ADC的指标实现,并对关键模块电路和ADC系统进行了仿真验证。A reconfigurable 14 bit and 100 MS/s pipelined ADC is proposed in this paper. To reduce the influence of non-ideal factors and achieve the design objectives, this paper has improved obviously on the design of some key units including sam-piing-and-hold circuit, bootstrapped switch, folded cascade amplifier and reconfigurable controller. The paper also discusses the sim-ulation of the key units and the system.

关 键 词：通信标准 可重构流水线ADC 栅压自举开关 非理想因素 仿真 

分 类 号：TN492[电子电信—微电子学与固体电子学]