Analysis of the dV/dt effect on an IGBT gate circuit in IPM  

作　　者：华庆 李泽宏 张波 黄祥钧 程德凯 

机构地区：[1]State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China [2]Midea Air-Conditioning & Refrigeration Research Institute

出　　处：《Journal of Semiconductors》2013年第4期64-68,共5页半导体学报（英文版）

基　　金：Project supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No. 2011ZX02504)

摘　　要：The effect ofdV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment. It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT. The dV/dt rate, gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike. The device with a higher dV/dt rate, gate-collector capacitance, gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on. By optimizing these parameters, the dV/dt induced voltage spike can be effectively controlled.The effect ofdV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment. It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT. The dV/dt rate, gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike. The device with a higher dV/dt rate, gate-collector capacitance, gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on. By optimizing these parameters, the dV/dt induced voltage spike can be effectively controlled.

关 键 词：IGBT dV/dt voltage spike IPM 

分 类 号：TN322.8[电子电信—物理电子学] S471[农业科学—农业昆虫与害虫防治]