Design of an unbuffered switch for network on-chip  

作　　者：刘浩 Cao Feifei Zhou Ning Zou Xuecheng Liu Dongsheng 

机构地区：[1]Henan Electric Power Research Institute [2]Henan Electric Power Industrial School [3]Department of Electronic Science & Technology,Huazhong University of Science & Technology

出　　处：《High Technology Letters》2013年第1期24-29,共6页高技术通讯（英文版）

基　　金：Supported by the National High Technology Research and Development Program of China(No.2009AA01Z105);the Ministry of EducationIntel Special Foundation for Information Technology(No.MOE-INTEL-08-05);the Postdoctoral Science Foundation of China(No.20080440942,200902432)

摘　　要：In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.In the complex multicore chip system, network on-chip （NoC） is viewed as a kind of system interconnection that can substitute the traditional interconnect networks, which will improve the system performance and communication efficiency. With regard to the complex and large scale NoC, simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion com- munication performance. This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture. According to the simulation results, the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures, such as 2D-mesh, Fat-tree, Butterfly, Octagon and so on. The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.

关 键 词：network on-chip （NoC） router architecture BUFFER LOW-COST 

分 类 号：TN47[电子电信—微电子学与固体电子学]