一种改进的低成本自适应双三次插值算法及VLSI实现  

An Improved Low-cost Adaptive Bicubic Interpolation Arithmetic and VLSI Implementation

作　　者：庞志勇[1,2] 谭洪舟[1] 陈弟虎[2] 

机构地区：[1]中山大学信息科学与技术学院,广州510275 [2]中山大学物理科学与工程技术学院,广州510275

出　　处：《自动化学报》2013年第4期407-417,共11页Acta Automatica Sinica

基　　金：广东省战略新兴产业关键技术产业化专项(2011168014;2011912004);广东省省部产学研重点科技项目(2011A090200037)资助~~

摘　　要：提出了一种新型图像缩放算法,由自适应锐化滤波器和双三次插值组成.锐化滤波器减轻了双三次插值产生的模糊效应,自适应技术进一步提升了图像缩放质量.为了减少运算量,提出前置滤波和后置滤波技术.与其他几种算法相比较,本文的算法在主观和客观评价方面都明显胜出.为了实现实时低成本设计,提出了一种该算法的流水线超大规模集成电路(Very large scale integration,VLSI)架构.在现场可编程逻辑器件(Field-programmable gate array,FPGA)上实现,占用695个逻辑单元(Logic elements,LEs),时钟频率达到165MHz,减少了36.8%逻辑单元,图像质量平均峰值信噪比(Peak signal-to-noise ratio,PSNR)提升了1.5dB.A novel scaling algorithm is proposed which consists of a bicubic interpolation and an adaptive sharpening filter. The proposed sharpening filter is added to mitigate the blurring effects existing in bicubic interpolation methods. We also verify the scaling quality by taking into account the adaptive technique. Furthermore, we present both the procedures of filtering before and after interpolation in order to reduce the overall computing time. Compared with the previous reported techniques, our method performs better in terms of both quantitative evaluation and visual quality. To achieve the goal of real time and low cost, we describe a pipelined VLSI architecture for the implementation of the algorithm. The very large scale integration （VLSI） architecture of our image scaling processor contains 695 logic elements （LEs） and yields a processing rate of about 165 MHz by using field-programmable gate array （FPGA） technology. Our proposed architecture reduces the amount of gates by 36.8 % while achieves an average peak signal-to-noise ratio （PSNR） increase of 1.5 dB in image quality.

关 键 词：双三次插值 图像缩放 拉普拉斯变换 自适应 超大规模集成电路 现场可编程逻辑器件 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]