NOVEL HIGH-SPEED FPGA-BASED FFT PROCESSOR  

作　　者：王旭东 徐伟 党小宇 

机构地区：[1]College of Electronic and Information Engineer,Nanjing University of Aeronautics and Astronautics

出　　处：《Transactions of Nanjing University of Aeronautics and Astronautics》2013年第1期82-87,共6页南京航空航天大学学报（英文版）

基　　金：Supported by the National Natural Science Foundation of China(60801052);the Aeronautical Science Foundation of China(2009ZC52036);the Ph.D.Programs Foundation of China's Ministry of Education(200802871056);the Nanjing University of Aeronautics & Astronautics Research Funding(NS2010109,NS2010114)

摘　　要：A novel architecture for computing the fast Fourier transform ( FFT ) on programmable devices is presented.To improve the system operation speed , a hybrid parallel FFT algorithm is used.Results indicate that the use of an 8×8parallel structure for realizing the 64-point FFT leads to a 8times higher processing speed compared with its counterparts employing other series of techniques.A novel architecture for computing the fast Fourier transform（FFT） on programmable devices is presen- ted. To improve the system operation speed, a hybrid parallel FFT algorithm is used. Results indicate that the use of an 8 ×8 parallel structure for realizing the 64-point FFT leads to a 8 times higher processing speed compared with its counterparts employing other series of techniques.

关 键 词：field programmable gate arrays ( FPGA ) fast Fourier transform ( FFT ) time-efficient hybrid parallel structure software define radio 

分 类 号：TN911[电子电信—通信与信息系统]