DTMB系统中BCH译码算法及其FPGA实现  

Decoding Algorithm and FPGA Implementation of BCH Codes in DTMB

作　　者：吴子静[1] 苏凯雄[1] 

机构地区：[1]福州大学物理与信息工程学院,福建福州350002

出　　处：《电视技术》2013年第9期142-145,152,共5页Video Engineering

基　　金：福建省科技重大专项专题项目(2010HZ0004-1)

摘　　要：首先证明了DTMB系统中采用的BCH码是纠错能力为1的循环汉明码,并基于此提出了适用于该BCH码的译码算法,及其串行和并行两种FPGA实现电路。考虑到该BCH缩短码的特性,通过修改差错检测电路,使其译码时延缩短34%。实验结果表明,译码器译码正确无误,FPGA资源占用极少。串行译码器总时延为762个时钟周期,最大工作时钟频率可达357 MHz。并行译码器总时延仅为77个时钟周期,最大工作时钟频率可达276 MHz。Firstly, the BCH codes used in DTMB system is a cyclic Hamming code is proved, whose correction capability is one bit. According to this, a decoding algorithm of the BCH codes is proposed. Then a serial decoder and a parallel decoder based on FPGA are designed. Taking into account the characteristics of the shorten BCH codes, the decoding delay of them is reduced by 34%. The implementation results show that the decoders decode cor- rectly and consume very little FPGA resources. The total delay of the serial decoder is 762 clock cycles, and the maximum clock frequency of that can reach 357 MHz. While the total delay of the parallel decoder is only 77 clock cycles and the maximum clock frequency of that can reach 276 MHz.

关 键 词：数字电视地面多媒体广播 BCH码 现场可编程门阵列 

分 类 号：TN911.22[电子电信—通信与信息系统] TN94[电子电信—信息与通信工程]