一种应用于LTE协议的高速ΣΔADC的降采样滤波器  

A Decimation Filter for High-speed ΣΔADC in LTE Protocol Application

作　　者：李婧[1] 李冉[1] 易婷[1] 刘洋 洪志良[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203 [2]美国ADI公司,上海200021

出　　处：《固体电子学研究与进展》2013年第2期183-188,共6页Research & Progress of SSE

基　　金：ADI公司资助项目;重点实验室自主资助项目(11MS002)

摘　　要：设计了一种应用于LTE协议的20 MHz带宽、12-bit精度ΣΔ模数转换器中的降采样低通数字滤波器,该滤波器采用一级梳状滤波器与两级半带滤波器级联的结构。基于低功耗设计考虑,降采样滤波器采用多相分解、CSD编码等技术,并对片内时钟偏差、串扰等进行优化以提高芯片的产率和可靠性。该设计在SMIC 00.13μm 1P8M标准CMOS工艺流片,测试结果表明芯片工作在11.2 V电源电压和500 MHz时钟频率时,在20 MHz的信号带宽内,带本滤波器的ΣΔADC的峰值SNDR和SNR分别为64.16 dB和64.71 dB,滤波器的功耗为4.8 mW。A decimation filter for 12-bit ∑△ADC over 20 MHz signal bandwidth is designed in LTE protocol application, which adopts a cascaded architecture of one comb filter and two half- band filters. Poly-phase decomposition and CSD coding techniques are utilized in order to reduce power consumption, and on-chip clock skew and crosstalk are optimized to improve the yield and reliability. This design is fabricated in SMIC 0. 13μmlP8M CMOS technology. The experimental results show that when clocked at 500 MHz,EAADC containing this design achieves peak SNDR and peak SNR of 64.16 dB and 64.71 dB over 20 MHz, respectively. And the decimation filter dissipates 4.8 mW at 1.2 V supply.

关 键 词：降采样滤波器 多相分解 CSD编码 片内时钟偏差 串扰 

分 类 号：TN713[电子电信—电路与系统]