众核处理器和众核集群的并行模拟  

Parallel Simulation of Many-Core Processor and Many-Core Clusters

作　　者：吕慧伟[1,2] 程元[1,2] 白露[1,2] 陈明宇[1] 范东睿[1] 孙凝晖[1] 

机构地区：[1]计算机体系结构国家重点实验室(中国科学院计算技术研究所),北京100190 [2]中国科学院大学,北京100049

出　　处：《计算机研究与发展》2013年第5期1110-1117,共8页Journal of Computer Research and Development

基　　金：国家自然科学基金项目(60633040;60925009;60921002;61173007);国家"九七三"重点基础研究发展计划基金项目(2011CB302501;2011CB302502);国家杰出青年科学基金项目(60925009);"核高基"国家科技重大专项基金项目(2011ZX01028-001-002)

摘　　要：模拟器是计算机体系结构研究的重要工具.近年来并行计算机体系结构的发展给计算机模拟带来了巨大的挑战.一方面,随着体系结构朝着多核以及众核处理器发展,模拟的目标系统规模随着模拟核数以摩尔定律的速度增加而不断增大;另一方面,串行模拟的速度因为模拟器运行所在宿主机主频提速减缓而停滞不前.上述两方面的原因使得传统的串行模拟方式无法满足对新兴体系结构模拟规模和速度的需求.以众核处理器和众核集群这两种体系结构为例,并行模拟技术在并行计算机体系结构模拟中是必要而且可行的.对于众核处理器的模拟,使用并行离散事件模拟对其进行加速,在模拟精度不变的前提下,提高模拟速度10.9倍.对于众核集群的模拟,模拟的目标系统总规模达到1024核,并且支持MPI/Pthreads混合编程的运行环境.Computer architecture simulator is an important tool for computer architecture researchers. Recent development of parallel architectures bring great challenge to computer simulations. On the target side, as processors move towards multi-core and many-core, the complexity of the target system is doubling in the speed of Moore＇s law as the simulated target core number grows; on the host side, the speed of sequential simulation is halted as the speed of a single host processor halts. Due to the above two reasons, sequential simulation could no longer meet the challenge of new parallel architectures. In this paper, we will describe the necessity and feasibility of parallel simulation for parallel computer architectures using two examples： a many-core processor simulator and a many-core cluster simulator. For many-core processor simulator, we use parallel discrete event simulation （PDES） to speed it up 10.9 times without accuracy lost. For many-core cluster simulation, we simulated a cluster at 1024-core scale, with MPI/Pthreads runtime support.

关 键 词：并行模拟 众核处理器 众核集群 众核模拟器 MPI Pthreads混合编程 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]