Matrix DSP中多线程机制的研究与设计  

Research and Design of Multiple Thread Mechanism in Matrix DSP

作　　者：邓宇[1] 孙永节[1] 万江华[1] 

机构地区：[1]国防科技大学计算机学院,长沙410073

出　　处：《计算机科学》2013年第4期51-54,共4页Computer Science

基　　金：国家"核高基"重大专项(2009ZX01034-001-006)资助

摘　　要：深入研究了YHFT_Matrix高性能DSP中的一种多线程机制,重点介绍了其循环指令缓冲的读写机制、单线程与多线程之间的模式切换机制。在基于65nm工艺下,经过综合,代码面积、功耗都有减少,关键路径优化0.07ns。对程序的执行评估测试的分析结果表明:多线程工作模式相比单线程工作模式,其处理器性能IPC(Instructions PerCycle)平均提高了9.64%。This paper presented the study of a multiple thread mechanism in YHFT_Matrix high performance DSP.It emphatically introduced the read and write mechanism of the loop instruction buffer and the mode switch mechanism between single_threaded and multithreaded.Based on the 65nm process,after being synthesized,both the code area and power consumption have been decreased,and the key path optimizes 0.07ns.The implementation of the program assessment test was analyzed,and the outcome shows that compared with the operation mode of single_threaded,the processor performance IPC（Instructions Per Cycle） has an average increasing of 9.64%.

关 键 词：多线程 循环指令缓冲 模式切换 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]