一种4Gb/s低压差分信号比较器的低抖动优化设计  

Design of a 4 Gb/s Low-Jitter/Low-Voltage Differential Signal Comparator

作　　者：韦雪明[1] 韦保林[1] 

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林541004

出　　处：《微电子学》2013年第2期225-229,249,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61166004;61264001)

摘　　要：基于低压差分信号比较器的结构,研究了影响比较器输出抖动的各种因素,并指出:根据差分信号的输入摆幅来优化电路有助于降低电路的输出抖动。基于0.13μm CMOS工艺,优化设计了一种低抖动的低压差分信号比较器电路。仿真结果显示,该低压差分信号比较器电路能够转换传输速率高达4Gb/s的信号,在输入信号差分摆幅确定的条件下,其额外引入的峰峰值抖动为2ps。Factors having effects on output jitter of low voltage differential signal（LVDS） comparator were investigated.Results showed that output jitter of the comparator could be reduced by optimizing the circuit according to differential swing voltage of the input signal.A low output jitter LVDS comparator was designed based on 0.13 μm CMOS process.Simulation results indicated that the circuit could convert signals up to 4 Gb/s,and it had an additional peak-peak jitter of only 2 ps for a certain differential swing voltage of input signal.

关 键 词：低压差分信号 抖动 差分比较器 

分 类 号：TN402[电子电信—微电子学与固体电子学]