一种带氧化槽的双栅LDMOS  

A Dual-Trench-Gate LDMOS with Oxide Trench

作　　者：臧凯旋[1] 方健[1] 吴杰[1] 贺雅娟[1] 陶垠波[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《微电子学》2013年第2期287-291,共5页Microelectronics

摘　　要：提出了一种带氧化槽的双栅体硅LDMOS结构(DGT LDMOS)。在漂移区中引入一个氧化槽,在该槽上形成埋栅,同时形成一个槽栅。首先,双栅形成双导电沟道,减小了比导通电阻;其次,氧化槽折叠了漂移区,这不仅调制了电场的分布,而且提高了漂移区的优化浓度,有效提高了击穿电压,降低了比导通电阻。采用二维数值仿真软件MEDICI,对器件参数进行仿真和优化设计。结果表明,相对于普通体硅LDMOS(SG LDMOS),该结构的比导通电阻下降了56.9%,击穿电压提高了82.4%。在相同尺寸和击穿电压下,相对于单槽栅体硅LDMOS(SGT LDMOS),DGTLDMOS的比导通电阻下降了35.4%。A double gate-trench LDMOS with oxide trench in bulk Si was proposed.In this structure,an oxide trench was inserted in the drift region;and a gate was buried in the oxide trench to form a gate-trench.The dual-gate formed a dual-conduction channel,which resulted in reduction of specific on-resistance.The oxide trench folded the drift region,which not only modulated distribution of electric field,but also optimized drift concentration of the drift region,leading to higher breakdown voltage and lower specific on-resistance.Parameters of the DGT LDMOS were optimized with 2-D MEDICI.Compared with SG LDMOS,DGT LDMOS reduced specific on-resistance by 56.9% and increased breakdown voltage by 82.4%.For the same size and breakdown voltage,DGT LDMOS had a specific on-resistance 35.4% lower than SGT LDMOS.

关 键 词：氧化槽 双栅 比导通电阻 LDMOS 功率器件 

分 类 号：TN43[电子电信—微电子学与固体电子学]