一种QAM符号定时算法  

A symbol timing algorithm for QAM

作　　者：李和[1] 莫金旺[1] 

机构地区：[1]桂林电子科技大学信息科技学院,广西桂林541004

出　　处：《兰州理工大学学报》2013年第2期102-105,共4页Journal of Lanzhou University of Technology

基　　金：广西教育厅科研项目(200911LX105)

摘　　要：针对目前从频域实现的锁相环提取同步信息的算法结构复杂的状态,提出一种在时域实现的正交幅度调制(QAM)符号定时方案:基于最大平均功率算法实现符号定时同步.通过对该算法的仿真研究,得到符号定时同步的FPGA实现方法,最后用Verilog HDL语言参数化设计方法实现符号定时同步模块的设计.对于QAM系统,利用该算法不需专门设计同步头即可为正确解调提供稳定可靠的符号定时同步信息.经实际验证,该算法稳定性很好,并且只在时域处理,省去了FFT变换,方便FPGA实现.Aimed at the complex status of present algorithm structure for extracting synchronization in- formation from phase locked loop in frequency domain, a symbol timing scheme was presented for realiza- tion of quadrature amplitude modulation （QAM） in time domain, namely implementing symbol timing synchronization with maximum/near/power algorithm. Then the FPGA implementation method was ob- tained by means of simulative investigation with above-mentioned algorithm. Finally, the designing of symbol timing synchronization module was realized with parameterized method in language of Verilog HDL. For a QAM system, this algorithm would be capable of providing stable and reliable symbol timing synchronization information for proper demodulation without specially designed pilot signal. It was justi- fied by practice that this algorithm was very stable and implemented in time domain only without EFT transformation, being convenient for FPGA implementation.

关 键 词：符号定时同步 最大平均功率算法 仿真研究 FPGA 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]