基于CPCI总线的FPGA加载设计  

Design of On-FPGA Loading based on CPCI Bus

作　　者：孟龙[1] 郄志鹏[1] 朱江[1] 

机构地区：[1]国防科技大学电子科学与工程学院,湖南长沙410073

出　　处：《通信技术》2013年第5期127-129,共3页Communications Technology

摘　　要：以现场可编程门阵列(FPGA,Field Programmable Gate Array)为核心的软件无线电平台在近年得到了广泛应用。由于具有极强的实时性和并行处理能力,FPGA芯片在无线通信、信号处理等领域得到了广泛应用。但是鉴于FPGA有易失性的特点,使得需要配备可擦可编程只读存储器(EPROM,ErasableProgrammable Read Only Memory)芯片对其进行加载。对于要求实时切换不同算法的应用场景,需要系统设计能够对FPGA进行动态加载。这里介绍了Xilinx系列FPGA的加载原理,基于紧凑型PCI(CPCI,CompactPeripheral Component Interconnect)总线设计,实现了对多片FPGA的动态加载。The software radio platform, with FPGA as its core is widely applied in recent years. For its strong real-time performance and parallel processing ability, FPGAchip is widely used in the fields of wireless communication, signal processing etc. However, due to its volatility, FPGA should be quiped with EPROM （Erasable Programmalbe Read-Only Memory） chip to facilitate its loading. However, for the application context demanding real-time switching-over of different algorithms, it is mecessary to make the system design capable of realizing dynamic on-FPGA loading. This paper describes the loading principle of FPGA under XILINX series and the implementation of dynamic loading on multiple FPGAs based on the designed CPCI bus.

关 键 词：CPCI PCI9656 现场可编程逻辑门阵列 动态加载 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]