CMOS宽带I/Q解调器的设计  

Design of CMOS Wide-Band I/Q Demodulator

作　　者：李国军[1] 刘利平[1] 

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050051

出　　处：《半导体技术》2013年第5期333-337,共5页Semiconductor Technology

摘　　要：设计了一款基于CMOS工艺的高动态范围宽带I/Q解调器。该解调器电路包括射频V/I转换电路、混频电路、中频缓冲电路,并且内部集成了高性能I/Q信号产生电路。此外,该解调器可以通过电流调控引脚对芯片工作电流进行调整从而实现三阶交调截取点和噪声系数的折中。该电路本振、射频端口可以工作在0.7-2.7 GHz范围内,在2.7 GHz工作频率下,输入三阶截点为26 dBm,噪声系数15.5 dB,1 dB压缩点输入功率为10.3 dBm。在5 V电源电压下,电流调控引脚悬空,芯片使能端有效的条件下,芯片工作电流为227 mA。该I/Q解调器电路采用0.35μm CMOS工艺设计,芯片面积约为3.8 mm2。A wideband high dynamic range CMOS I/Q demodulator was designed, which comprised of radio frequency voltage to current conversion circuit, the mixer circuit, the intermediate frequency amplifier, and a high performance I/Q signal generator. In addition, current of the demodulator can be adjusted, through which one can trade off the noise figure with the third order intermodulation intercept point according to the specified situation. Both the radio frequency port and the local oscillator port can operate in the frequency range of 0.7 -2.7 GHz. The input third order intercept point is 26 dBm, the single sideband noise figure （SSB） is 15.5 dB, and the input 1 dB compression point is 10.3 dBm at frequency of 2.7 GHz. Under a supply voltage of 5 V, the current is 227 mA when the enable pin of the chip is effective and letting the current adjusting pin floating. The demodulator is implemented in O. 35 Ixm CMOS process and occupies an area of 3. 8 mm2.

关 键 词：I/Q解调器 混频器 三阶交调截取点 I/Q信号发生器 CMOS 

分 类 号：TN492[电子电信—微电子学与固体电子学] TN76