基于CoreConnect的OPB SPI接口设计与实现  

Design and Realization of OPB SPI Interface Based on CoreConnect

作　　者：王宏亮[1] 毛永毅[2] 张宏君[1] 

机构地区：[1]西安邮电大学通信与信息工程学院,陕西西安710061 [2]西安邮电大学电子工程学院,陕西西安710061

出　　处：《测控技术》2013年第5期72-76,共5页Measurement & Control Technology

基　　金：陕西省自然科学基金资助项目(2009JM8015);陕西省教育厅专项科研项目(2010JK815)

摘　　要：针对SPI接口传输速率低、CPU利用率低、主从机配置固定和从机选择单一等问题,提出一种基于CoreConnect总线的OPB SPI接口设计方案。添加缓冲FIFO、SCK时钟波特率寄存器、连续发送间隔寄存器,采用可扩展从机模式,设计出传输高效、主从灵活可配、多从机选择可配的OPB SPI接口。仿真测试表明该接口的有效性和可行性,能够满足SOC系统的需要。According to the problems of SPI interface such as low transmission rate, low CPU utilization effi- ciency, the fixed master-slave machine configuration and choosing from a single machine, a OPB SPI interface design based on CoreConnect is proposed. Buffer FIFO, SCK clock baud rate registers and continuous sending interval registers are added, expanded slave model is used, OPB SPI interface is designed, whose transmission efficiency is high, master-slave can be configured flexibly, multi-slave selection model can be matched with the OPB SPI. The simulation results show that the designed interface has high effectiveness and feasibility, and can satisfy the needs of SOC svstem.

关 键 词：CoreConnect总线 OPB总线 SPI接口 系统级芯片 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]