双面蚀刻薄介质材料埋容芯板可行性研究  

Research on the Feasibility of Thin Film Capacitance Material with Double-side-etch Process

作　　者：范海霞[1] 王守绪[1] 何为[1] 董颖韬[1] 胡新星 苏新虹 刘丰 

机构地区：[1]电子科技大学,四川成都610054 [2]珠海方正印刷电路板发展有限公司,广东珠海519173

出　　处：《印制电路信息》2013年第5期76-79,共4页Printed Circuit Information

摘　　要：用蚀刻薄膜材料法制作埋嵌式电容,其电容介质材料较薄,常用的电容介质材料厚度在8 m～50 m之间,因此在制作电容层图形时,容易出现皱折、破损的情况。目前可行的方法是用单面蚀刻法制作电容层图形。探讨运用双面蚀刻法制作电容层图形对电容值精度的影响及其可行性分析。The embedded capacitor is made by means of etching thin-film dielectric material, and the thickness of the material is very thin. Thickness of dielectric material is almost between 8μ m and 50μm, therefore, it＇s easy to fold and break the core when pattern imaging. At present, the most practicable method is single-sideetch process. This paper discuss the influence of capacitance accuracy and reliability of capacitance material when double-side-etch process is adopted which results in the analysis of the feasibility of this process.

关 键 词：埋嵌电容 薄介质 双面蚀刻 

分 类 号：TN41[电子电信—微电子学与固体电子学]