基于FPGA高速线阵CCD的驱动电路设计  

Design of the driving circuit of the linear array CCD based on FPGA

作　　者：喻依虎[1] 孟丽娅[1] 岳陈平[1] 

机构地区：[1]重庆大学光电技术及系统教育部重点实验室,重庆40030

出　　处：《微型机与应用》2013年第10期26-28,共3页Microcomputer & Its Applications

基　　金：重庆市自然科学基金支持项目(CSTC;2010BB0075)

摘　　要：线阵CCD的驱动电路设计是决定CCD成像质量的关键技术之一。在对TCD1706D线阵CCD驱动时序分析的基础上,利用FPGA实现了线阵CCD的工作频率为10MHz的驱动电路设计。利用QuartusⅡ软件自带的PLLIP核生成系统工作频率,通过Verilog语言对硬件电路进行描述,采用Moore有限状态机实现驱动信号之间的相位关系。通过QuartusⅡ软件平台,对设计的时序电路进行仿真,并在示波器中显示了直径为0.16mm的漆包线的成像波形。实验结果表明,该方法能够满足TCD1706D线阵CCD工作频率为10MHz的要求。The design of the driving circuit of the linear array CCD is one of the crucial technology which determines the imaging quality. Based on the analysis of the driving schedule of the TCD1706D linear array CCD, the design of the driving circuit of the linear array CCD whose operating frequency is 10 MHz is achieved by utilizing FPGA. In the whole process, operating fre- quency is generated by utilizing the phase-locked loop coming with Quartus II; hardware circuit is depicted by using Verilog lan- guage; phase relation among the driving signal is achieved by adopting the Moore finite state machine. The result of the test, which simulates the designed driving schedule in Quartus II and shows the imaging waveform of enameled wire which diameter is 0.16 mm in the oscilloscope, indicates that the adopted method can meet the requirement of the TCD1706D linear array CCD whose operating frequency is 10 MHz.

关 键 词：FPGA 锁相环 线阵CCD 

分 类 号：TN784[电子电信—电路与系统]