高阶多位∑-Δ调制器设计方法研究  

Research on Design Method of High-Order Multi-Bit ∑-ΔModulators

作　　者：于泽琦[1] 樊养余[1] 冯晖[2] 吕国云[1] 

机构地区：[1]西北工业大学电子信息学院,陕西西安710129 [2]同济大学超大规模集成电路研究所,上海201804

出　　处：《计算机仿真》2013年第5期239-242,318,共5页Computer Simulation

基　　金：陕西省科学技术研究发展计划项目(2012K06-10);上海自然科学基金(11ZR1440300)

摘　　要：∑-Δ调制器作为数字D类功放的一个重要模块,性能的高低直接影响着数字D类功放的总体性能。针对目前所存在的高阶多位∑-Δ调制器的噪声传递函数(NTF)设计方法对最大稳定输入幅度所产生的限制条件比较苛刻,造成所设计的NTF往往不是最优的情况,提出一种基于多变量优化理论和新的稳定性判定方案的高阶多位∑-Δ调制器NTF设计方法,并设计了一个用于数字D类功放的8阶5位∑-Δ调制器。仿真结果表明,多位∑-Δ调制器性能优于使用传统设计方法设计的∑-Δ调制器,完全满足高性能数字D类功放需求。∑-△ modulator is a very important module in digital class D power amplifiers. Its performance can di- rectly influence the performance of digital class D power amplifiers. Because the existing design methods of noise transfer function （NTF） of high-order multi-bit ∑-△ modulator are strict about constraint conditions produced by maximum-stable-input-amplitude, the NTFs designed by these methods are always not optimal. A high-order multi -bit ∑-△ modulator NTF design method based on multivariable optimization theory and a new stability decision scheme was presented in this paper. Based on this method, an 8-order 5-bit ∑-△ modulator was designed and simulated. The simulation results indicate that its performance is better than the performance of the ∑-△ modulators designed by traditional methods and is enough to suit the need of high-performance digital class D power amplifier.

关 键 词：调制器 数字功放 噪声传递函数 多位 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]