基于VHDL的简易数字频率计的设计  

Designing a simple digital frequency meter based on VHDL

作　　者：张博[1] 曹学岩[1] 房亮[1] 

机构地区：[1]中北大学机械工程与自动化学院,山西太原030051

出　　处：《传感器世界》2013年第5期29-34,共6页Sensor World

摘　　要：本论文采用自上向下的电子系统设计方法,基于VHDL硬件描述语言设计了一种可变换量程的数字频率计,并在QuartusⅡ平台上进行仿真,在F10K10M试验箱上进行了下载验证。数字频率计的模块划分设计具有相对独立性,可以对每个模块单独进行设计、调试仿真和修改,缩短了设计周期,减小了设计复杂度。仿真波形逻辑关系与试验箱测试结果表明,所设计的电路能够满足数字频率计的功能要求,具有理论与实践意义,实现了电子电路自动化过程。Using the top-down design method of digital system, a variable-rang digital frequency meter is designed based on VHDL and then simulated on Quartus II platlbnn, verified on F10k10M testbox in this paper. The digital frequency meter is relative independent in module design to ensure designing, debugging and modifying every modules independently, which can shorten the design cycle and reduce the design complexity effectively Simulation analysis results show that the system can meet the design requirements of measurement error less than or equal to 1% and realize the electronic circuit automation process.

关 键 词：CPLD芯片 VHDL语言 数字频率计 QuartusⅡ软件 

分 类 号：TM935.133[电气工程—电力电子与电力传动]