ReSSIM:a mixed-level simulator for dynamic coarse-grained reconfigurable processor  

作　　者：LIU LeiBo JIA Wen YIN ShouYi WANG Dong SUN GuanYi TANG Eugene WEI ShaoJun 

机构地区：[1]Institute of Microelectronics and National Laboratory for Information Science and Technology,Tsinghua University [2]Intel China Research Center

出　　处：《Science China(Information Sciences)》2013年第6期133-148,共16页中国科学（信息科学）（英文版）

基　　金：supported in part by National High-tech R&D Program of China (863 Program) (Grant No.2009AA011702)

摘　　要：This paper proposes a mixed-level simulator for dynamic coarse-grained reconfigurable processor（CGRP）,called ReSSIM（reconfigurable system simulation implementation mechanism）,and the corresponding simulation tool-chain,including task compiler,profiler and debugger.A generic modeling methodology supporting convenient extension of on-chip modules is also proposed.In order to explore the details of the interested modules while maintaining reasonable simulation speed,RCA（reconfigurable computing array）,the key reconfigurable device in ReSSIM,is modeled on cycle-accurate level,while the other modules are modeled on transaction level.The typical parameters of RCA are scalable and adjustable,which helps the architects to explore the massive details of the reconfigurable device.Experiment shows that simulation speedup achieved ranges from 9.26× to 18.39× compared with VCS（Synopsys verilog compiler simulator） when running three computingintensive kernel tasks of H.264 decoding algorithm-IDCT（inverse discrete cosine transform）,deblocking and MC-chroma（motion compensation）.Simulation speed for a set of real applications,such as MPEG4,G.729 and EFR,is 35× slower than the corresponding native executions（i.e.measured from the real chip）.And the relative simulation errors are 11% less than the measured IPC（instructions per cycle） of the real chip.This paper proposes a mixed-level simulator for dynamic coarse-grained reconfigurable processor（CGRP）,called ReSSIM（reconfigurable system simulation implementation mechanism）,and the corresponding simulation tool-chain,including task compiler,profiler and debugger.A generic modeling methodology supporting convenient extension of on-chip modules is also proposed.In order to explore the details of the interested modules while maintaining reasonable simulation speed,RCA（reconfigurable computing array）,the key reconfigurable device in ReSSIM,is modeled on cycle-accurate level,while the other modules are modeled on transaction level.The typical parameters of RCA are scalable and adjustable,which helps the architects to explore the massive details of the reconfigurable device.Experiment shows that simulation speedup achieved ranges from 9.26× to 18.39× compared with VCS（Synopsys verilog compiler simulator） when running three computingintensive kernel tasks of H.264 decoding algorithm-IDCT（inverse discrete cosine transform）,deblocking and MC-chroma（motion compensation）.Simulation speed for a set of real applications,such as MPEG4,G.729 and EFR,is 35× slower than the corresponding native executions（i.e.measured from the real chip）.And the relative simulation errors are 11% less than the measured IPC（instructions per cycle） of the real chip.

关 键 词：CGRP RCA ReSSIM modeling SIMULATOR 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]