祖冲之算法分析及其硬件实现  

Analysis and Hardware Realization of ZUC Algorithm

作　　者：任高峰[1] 乔树山[1] 黑勇[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《电视技术》2013年第11期79-82,93,共5页Video Engineering

基　　金：国家自然科学基金项目(61102072);"核高基"重大专项(2009ZX01034-002-004-007(002))

摘　　要：详细分析了3GPP LTE国际加密标准祖冲之(ZUC)算法的结构及其硬件实现过程。ZUC流式加密算法采用了线性反馈移位寄存器(LFSR),比特重组(BR)和非线性函数F的三层结构设计,具有很高的安全性。同时,ZUC算法在设计时就充分考虑了软硬件实现的低复杂度,因此非常适合于硬件实现。ZUC算法在Altera的Cyclone FPGA上实现,需要2 013个逻辑单元,不需要存储器。在中芯国际SMIC 0.18μm的CMOS工艺上实现的芯片面积为109 823μm2。In this paper, the architecture and hardware realization of the ZUC algorithm are presented. The ZUC algorithm is accepted by the 3GPP LTE as the international encryption standard for the 4G mobile communication. The ZUC algorithm is a stream cipher technique with high security for its three logic layers structure of Linear Feedback Shift Register, bit reorganization and nonlinear function. What＇s more, the ZUC algorithm is easy to be realized by hardware. It will cost 2 013 logic elements and without memory when the ZUC algorithm is implemented in the Altera Cyclone FPGA.The chip area is 109 823μm2 when the ZUC algorithm is implemented in the CMOS technology of SMIC 0.18 μm.

关 键 词：祖冲之算法 线性反馈移位寄存器 比特重组 非线性函数 FPGA ASIC 

分 类 号：TN918.91[电子电信—通信与信息系统]