一种面向HEVC运动估计的高性能VLSI架构  

High Performance VLSI Architecture for HEVC Motion Estimation

作　　者：陈伟伟[1] 朱惠[1] 何卫锋[1] 毛志刚[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《微电子学与计算机》2013年第6期10-14,共5页Microelectronics & Computer

摘　　要：HECV是正在开发的下一代视频编码标准.为了进一步提高视频图像的压缩效率,HEVC中引入了不对称划分模式,且最大编码单元达到64×64像素.针对HEVC标准,提出了一种面向超高清视频图像应用的高性能运动估计VLSI架构.该VLSI架构能够支持从4×4到64×64的849种块的划分种类,其中包括168种不对称划分,并可重构支持3种搜索区间.通过层次化数据重用策略和存储访存策略,与传统设计相比将片外数据带宽减少了99.2%.采用TSMC 90nm工艺综合,该电路的最高工作频率可达到330MHz,电路规模86万门,功耗229mW.仿真结果表明,在280.4MHz工作频率下,能够完成超高清视频图像3 840×2 160p,30f/s的实时编码要求.High Efficiency Video Coding （HEVC） is the next generation video coding system under standardization. HEVC employs the Largest Coding Unit （LCU） up to 64 × 64 pixels with Asymmetric Motion Partitions （AMP）, which significantly increases the algorithm complexity of Motion Estimation （ME）. In this paper, a novel VLSI architecture compatible to HEVC ME algorithm is proposed for the first time. A quarter of LCU size＇s Processing Element （PE） array architecture is adopted to conduct full search ME with 849 different block sizes from 4× 4 to 64 × 64 pixels, 168 AMPs such as 4 × 16 and 24 N 32 pixels, as well as 3 search ranges （SR） including F-4,4）, [-8,8） and [-16,16） pixels. Moreover, a hierarchy data reuse scheme and a memory access strategy are adopted to reduce off-chip bandwidth up to 99. 2% compared to the traditional method. Using TSMC 90 nm 1P9M technology, the proposed architecture is synthesized at the maximum work frequency of about 330 MHz with 860 ×10a Gates and 229 mW. Simulation results show that the architecture is able to process 3 840× 2 160 p video at 30 f/ s at nearly 280. 4 MHz.

关 键 词：HEVC 视频编码 运动估计 VLSI 

分 类 号：TN402[电子电信—微电子学与固体电子学]