2D图形加速器设计与实现  

Design and Implementation of 2D Graphics Accelerator

作　　者：刘鑫[1] 蒋林[1] 

机构地区：[1]西安邮电大学研究生学院,陕西西安710061

出　　处：《微电子学与计算机》2013年第6期75-79,共5页Microelectronics & Computer

基　　金：国家自然科学基金面上项目"三维视频处理系统芯片动态可重构可编程体系结构研究"(61272120)

摘　　要：设计并实现了2D(2Dimensional)图形加速器电路,提供基本图元:点、线、多边形的绘制,及任意大小和颜色的字符显示.采用流水线结构,流水线各级间采用握手信号进行信息交互,缩短了处理时间,提高了工作效率,也便于各子模块间的时序配合.对常用的两种二维绘图算法进行研究,使用Verilog HDL硬件描述语言实现2D图形加速器的硬件电路.与System Verilog搭建的电路行为模型对比仿真,输出的图形数据信息结果一致,并在FPGA上进行验证.采用SMIC 0.13μm标准CMOS工艺库综合,工作频率达205MHz.This paper designs and implements the 2D （2 Dimensional） Graphics Accelerator circuit. It provides the basic primitives point, line, polygon, and displays the words with any size and color. A pipeline architecture is used in the design. To exchange information handshake signals is used between the pipeline stages. It not only shortens the processing time and improves work efficiency, but also facilitates the co-ordination of the timing between the various sub-modules. The paper studies two kinds of high-frequency algorithms, uses the Verilog HDL language to describe 2D Graphics Accelerator hardware circuit. Compared with the simulation results of the behavior model, which is built by SystemVerilog, the results are consistent, and implements on FPGA. The operating frequency can reach 205 MHz with SMIC 0. 13 μm standard CMOS cell library.

关 键 词：2D图形 字体 ROP2操作 FPGA 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]