An Improved Current Mode Logic Latch  

作　　者：ZHANG We ZHANG Liang ZHANG Xu MA Xuepo LIU Yanyan 

机构地区：[1]School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China [2]College of Information Technical Science, Nankai University, Tianjin 300071, China

出　　处：《Chinese Journal of Electronics》2013年第1期214-218,共5页电子学报（英文版）

摘　　要：In order to reduce power consumption and additional chip area, an improved Current mode logic （CML） latch, which can work at a lower power supply with-out the level shifter, is presented. To compensate the speed loss caused by large voltage swing, a cross coupled pair is added to the load of the latch. A simplified model which divides operating situation into different phases is built to illustrate the operating principle of the structure and optimize the speed of the circuit. Further analysis also indicates that the latch can work at a much lower volt-age supply. The proposed divider has been used in a fre-quency synthesizer. Measurements were made to support above features. It has been proved that the structure in this work has more advantages than the conventional ones.

关 键 词：Current mode logic （CML） Low powersupply High speed divider. 

分 类 号：TN713[电子电信—电路与系统] N02[自然科学总论—科学技术哲学]