一种新的NIOS-Ⅱ Turbo解码器硬件加速方案  

A new NIOS-II turbo decoder hardware acceleration program

作　　者：陈向华[1] 周娟[2] 

机构地区：[1]成都工业学院计算机工程系,四川成都611730 [2]成都工业学院组织部,四川成都611730

出　　处：《西南民族大学学报（自然科学版）》2013年第3期470-476,共7页Journal of Southwest Minzu University(Natural Science Edition)

摘　　要：提出了一种基于硬件加速的NIOS-ⅡTurbo解码器的实现．该方案首先构建了由两个并行级联的RSC编码器组成的编码器和由两个相同的SOVA解码器组成的解码器所构成的Matlab原型，仿真结果表明解码器中误码率在每次迭代中都有下降（下降至10-4），除了低信噪比情况（低于-5dB）．然后，描述并比较了两种基于FPGA实现的解码器．第一种是由一个运行在NIOSⅡ快速型软核处理器的软件实现，第二种是在第一种方案中加入了硬件加速器．从硬件解码过程加速实施的结果来看，BER大致和软件解码实现相同，但执行时间减少了25％～34％，当解码迭代的次数增加l至20时。与软件解码实现相比，硬件加速的方法对资源的需求增加了10％～16％．This paper presents a hardware accelerated NIOS-II Turbo decoder implementation. The programme is first constructed by two parallel cascade RSC encoders and consists of two identical SOVA decoders of Matlab prototype. Simulation results show that the decoder bit error rate in each iteration is reduced （down to 10-4）, except for the low SNR （less than -5dB）. Then two FPGA-based decoders are described and compared. The results show the execution time is reduced by 25%-34%, and, when the decoding iteration number is increased from 1 to 20, compared with software decoder implementation, the demand for resources by hardware acceleration methods is increased by 10%-16%.

关 键 词：Trubo解码 FPGA 软核处理器 NIOS-Ⅱ硬件加速 并行 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]