基于FPGA的改进积分型位同步环设计  

Design of improvement integral bit synchronization loop based on FPGA

作　　者：杜勇[1] 刘帝英[1] 罗宇智[1] 

机构地区：[1]酒泉卫星发射中心,甘肃酒泉732750

出　　处：《信息技术》2013年第5期129-132,136,共5页Information Technology

摘　　要：介绍了积分型位同步环的原理。针对相位抖动的问题,提出了积分型位同步环的改进方案。采用模块化的设计思想,利用VHDL语言设计了改进的积分型位同步环,并在Xilinx的FPGA器件XC3S200-4FT200上进行了实现。利用Modelsim6.0软件对改进前后的位同步环进行了仿真测试,仿真结果表明,改进的位同步环可有效减少相位抖动,满足性能要求。The principle of integral bit synchronization loop is described in this paper. An improvement scheme is put forward to solve the problem of phase jitter. Modular programming is used in the design of integral bit synchronization loop using VHDL, and the loop is implemented on XC3S200-4FT200 of FPGA in Xilinx. Using Modelsim6.0 software carries out the simulation test of the two kinds of bit synchronization loop, the simulation results indicate the improvement system can reduce the phase jitter effectively and meet the performance requirements.

关 键 词：位同步 FPGA VHDL语言 

分 类 号：TN914[电子电信—通信与信息系统]