一种低功耗低偏斜的无缓冲谐振时钟分布网络设计  

Design of bufferless resonant clock distribution network with low power and Low skew

作　　者：徐毅[1] 陈书明[1] 刘祥远[1] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2013年第5期9-14,共6页Computer Engineering & Science

基　　金："核高基"重大专项资助项目(2009ZX01034-001-001-006);国家863计划资助项目(2009AA011704);国家自然科学基金资助项目(60906014)

摘　　要：作为下一代时钟分布技术的有力竞争者,谐振时钟机制具有低功耗、低偏斜的显著优势,但设计方法的缺乏导致该技术在同步数字系统中的应用受到严重制约。为解决这一问题,提出了一种面向无缓冲谐振时钟分布技术的物理设计方法,能够结合现有设计流程,有效实现谐振时钟网络设计。该方法基于SPICE分析并优化与谐振时钟网络相关的设计参数,保证整个物理设计快速收敛于目标频率。通过一块乘法器电路验证了该设计方法,带有寄生参数网表的SPICE结果显示,与采用树型和网格型时钟分布网络的同步电路相比,基于无缓冲谐振时钟网络的同步电路时钟系统功耗降低最高可达64%,总功耗降低16%以上。此外,无缓冲时钟网络的时钟偏斜小于时钟周期的2%。As the powerful competitor of the next generation clock distribution technology, resonant clock scheme shows obvious advantages in low power consumption and low skew. But the application of this technology is limited because of the absence of a systematic design methodology. To solve the problem, a physical design method of bufferless resonant Clock Distribution Network （CDN） was proposed in this paper. The method uses the conventional synchronous design flow and implements resonant clock network efficiently. Based on SPICE analysis and optimization for the design parameters of the resonant CDN, the proposed method makes the physical design converge fast at the target frequency. A multiplier circuit was designed using this method, and the results of post--layout SPICE show that, compared with the synchronous design employing tree-based and mesh-based CDN, the bufferless resonant CDN based circuit can save CDN power up to 64% and total power up to 16%. Additionally, the clock skew in resonant CDN is less than 2 % of clock cycle under different process corners.

关 键 词：时钟分布网络 谐振时钟 设计方法学 低功耗 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]