PABLE:一种异步总线的设计与实现  

Design and implementation of an asynchronous bus : PABLE

作　　者：张光达[1] 王友瑞[1] 石伟[1] 王志英[1] 陆洪毅[1] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2013年第5期34-40,共7页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(60873015);国防科技大学优秀研究生创新资助项目(S100605)

摘　　要：异步电路能够解决同步电路中时钟偏移、功耗过高等问题,且具有平均情况下的性能。为了实现芯片上异步模块之间的全异步通信,发挥异步电路功耗与性能上的优势,设计了一款部分兼容AMBA AHB总线协议的异步总线PABLE。通过使用流水线结构提高总线性能,并着重研究异步仲裁电路,最终采用解同步的异步电路设计方法对PABLE进行了实现。实验结果表明,在UMC 0.18μm CMOS工艺下,对于单次数据读写操作,在大于60%的情况下,PABLE总线的读写延迟要低于同步总线;与相同功能的同步总线相比较,PABLE总线的平均功耗下降了约41%。Asynchronous circuit can resolve clock-caused problems in synchronous circuits, such as clock skew and high energy dissipation, attracting increasing attention. In order to implement full asynchronous communication among asynchronous modules on a chip and take advantage of asynchronous circuits in power consumption and performance, the paper designed an asynchronous bus PABLE （pipelinebased asynchronous bus for low energy）, which is partially compatible with the synchronous AMBA AHB protocol and uses the asynchronous pipeline to improve the performance. Asynchronous arbitration circuit was designed, which can eliminate meta-stability. Finally, the desynchronization method was adopted to implement the PABLE. Results of the experiment show that, under the UMC 0.18urn CMOS technology, for a single read or write operation, the read or write latency of the PABLE is lower than the synchronous bus in more than 60% cases and its average power consumption decreases by 41% compared with the synchronous bus.

关 键 词：异步总线 流水线 仲裁器 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]