一种改进的测试芯片的设计方法  

An improved method for test chip design

作　　者：潘伟伟[1] 张波[1] 郑勇军[1] 史峥[1] 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路研究所,浙江杭州310027

出　　处：《电路与系统学报》2013年第2期331-336,共6页Journal of Circuits and Systems

基　　金：国家"十一五"高端通用芯片科技重大专项基金资助项目(2008ZX01035-001-06)

摘　　要：集成电路制造技术的不断进步,给缺陷定位带来巨大的挑战。传统的测试芯片和现有的可寻址的方法都无法满足当前缺陷快速准确定位的要求。本文提出了一种改进的可寻址测试芯片的设计方法:每个测试结构采用四端法连接以及单一的NMOS晶体管作为开关电路,以保证电性测量结果精确、电路设计的简洁以及面积利用率的进一步优化;并利用开关电路增加少量测试引脚,以方便物理缺陷定位的进行。该方法在110nm的CMOS工艺中得到应用。经过实际生产验证,实现了金属层断路等缺陷的定位,有效发现了该工艺中失效缺陷的成因,从而帮助实际的成品率实现快速提升。The rapid development of IC manufacturing technology poses huge challenges to localize an electrical defect to a specific area on the IC.Either traditional or existing addressable design methods of test chip fail to fulfill the current requirements for fast and accurate defect localization.In this paper,we present an improved method for addressable test chip design.For electrical testing of test chip,four-terminal connection of each test structure and single NMOS transistor as switch are used to improve measurement accuracy,peripheral circuits design simplicity as well as area efficiency.For defect localization,only a small amount of pads are added and used together with switches to localize physical faults.This method is used in a 110nm CMOS technology and verified by the silicon results,which shows several real defects（metal open,etc） are localized to help determine the physical root causes and realize a rapid yield improvement.

关 键 词：测试芯片 可寻址 失效分析 缺陷定位 

分 类 号：TN406[电子电信—微电子学与固体电子学]