基于模块化单元的测试结构阵列设计及其应用  

Design and application of test structure array based on modular unit

作　　者：张波[1] 潘伟伟[1] 叶翼[1] 郑勇军[1] 史峥[1] 严晓浪[1] 

机构地区：[1]浙江大学超大规模集或电路设计研究所,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2013年第5期837-842,852,共7页Journal of Zhejiang University：Engineering Science

基　　金：国家自然科学基金资助项目(61106034);国家重大科技专项资助项目(2009ZX02023-004-1)

摘　　要：针对纳米级半导体制造工艺中传统测试芯片掩模面积利用率低的问题,提出一种基于模块化单元的可扩展成品率测试结构阵列设计方法.基于45nm CMOS制造工艺分别实现32×32和64×64 2个大规模的测试结构阵列,模块化单元的有效面积利用率达79.31%和70.8%;流片后通过测试数据的分析能够发现通孔缺失、通孔尺寸变大以及大尺寸缺陷导致金属缺失等工艺缺陷问题.试验结果同时表明,该方法将传输门器件和测试结构组合成模块化单元;不仅能够实现对测试结构的四端测量,保证测试结果的正确性,并且能够减小成品率测试芯片的掩模面积.A modular unit based design method of scalable test structure array is presented, aiming to increasing mask utilization ratio of test chips in nanometer scale IC manufacturing. Implemented in 45 nm CMOS technology, two large-scale test structure arrays, with 32× 32 and 64 × 64 units respectively, had been designed and fabricated as the experiments. By combining the device-under-test （DUT） and the transmission gates into one standard modular unit, the area utilization reached 79.31% and 70.8% for these experiments. Process defects such as via-induced metal loss were reported after testing data analysis. The results demonstrated that the process window could be sufficiently tracked with those arrays, which further proves the accuracy and effectiveness of the presented design method.

关 键 词：集成电路 纳米级工艺 成品率 测试结构阵列 掩模面积 测试芯片 

分 类 号：TN43[电子电信—微电子学与固体电子学]