多通道ADC的高速接口设计  

Design on Multichannel ADC High-speed Interface

作　　者：屈超[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081

出　　处：《无线电通信技术》2013年第3期76-78,共3页Radio Communications Technology

摘　　要：针对多通道高速采样器ADS6445的高速串行数据接口特点,提出了一种高速接口的实现方法。使用Xilinx Vertex5系列FPGA接收采样串行数据,利用FPGA的片同步技术通过在线时序调整实现了高速解串;对高速接口的组成及工作原理、片同步技术的特点、设计规则进行了简要介绍,描述了高速接口的时序调整过程;对高速接口的适应能力进行了分析,最后通过仿真及试验验证了接口工作的正确性。Aiming at the characteristics of high-speed serial data in muhi-channel sampler ADS6445, a method of high-speed interface is presented. In this method, the Xilinx Vertex5 family FPGA is used to receive the sampling serial data and the FPGA ChipSync technology is used to deserialize the data at high-speed by online time sequence adjustment. The paper describes the composition and working principle of system, the characteristics of ChipSync, the design rules of circuit, and the process of time sequence adjustment. The adaptability of high-speed interface is analyzed and the working of interface is validated by simulation and experiment finally.

关 键 词：片同步 多通道ADC 高速接口 SERDES FPGA 

分 类 号：TN919.3[电子电信—通信与信息系统]