WEP安全组件的FPGA实现与优化  

Implementation and Optimization of WEP Encrypt and Decrypt Module Based on FPGA

作　　者：向伟 沈诗律[2] 查智 耿文豹 

机构地区：[1]中国船重工710所 [2]西北工业大学 [3]中船重工710所

出　　处：《微型电脑应用》2013年第5期4-6,共3页Microcomputer Applications

基　　金：国家863高技术研究发展计划资助项目(NO.2012AA090901-05)

摘　　要：针对有线等效加密(WEP)安全组件高速率,低延迟的需求,提出了一种用Verilog硬件描述语言,基于FPGA平台实现IEEE 802.11a标准中,媒体访问控制(MAC)协议的WEP安全组件的方案,并通过改进架构的方式,对WEP模块的性能做了优化设计,将延迟减小到最低,使模块速率满足802.11最高速率54Mbps的要求。性能测试表明,该方案满足IEEE 802.11a标准需求,在无线通信领域具有较高实用性。Differing from the demand of WEP module for high speed and low delay, a method to implement and optimize the WEP encrypt and decrypt module with VerilogHDL base on FPGA according to IEEE 802.11a Standard is proposed. The delay of the moduleis reduced by improving the architecture, as a result, the running speed meets 802.1 la＇s highest rate of 54Mbps. Performance test verifies that this proposal is qualified for IEEE 802.11a＇s WEP encryption and decryption, and is practical for wireless commu- nication applications.

关 键 词：WEP FPGA 无线局域网 优化 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]