基于竞争-冒险的卡诺图在组合逻辑电路中的应用  

The application of Karnaugh Map Based on the Competition and Hazard to Combinational Logic Circuits

作　　者：董金明[1] 黄福[1] 

机构地区：[1]安阳师范学院人文管理学院,河南安阳455000

出　　处：《安徽电子信息职业技术学院学报》2013年第3期18-20,共3页Journal of Anhui Vocational College of Electronics & Information Technology

摘　　要：在组合逻辑电路中竞争是一种特有的现象,该现象是由同一输入信号经过不同的逻辑门电路后到达同一终点时产生的延迟时间差造成的,而竞争现象的发生往往容易引起冒险现象的发生。因此,在对组合逻辑电路进行设计时,应尽量避免电路中出现竞争冒险现象,因为它会导致组合逻辑电路在逻辑设计上虽然准确无误,但是会在实际的调试运行过程中得到错误的结果。文章在对竞争冒险现象产生的原因,识别方法分析的基础上,介绍了一种简单易操作的卡诺图法来识别和清除竞争冒险现象。Competition is a unique phenomenon in the combinational logic circuit.The phenomenon is caused by the delayed time difference when the same input signal,after different logic gate circuits,reaches the same end,and the occurrence of competition tends to lead to hazard.Therefore,when the combinational logic circuit is designed,the competition-hazard in the circuit should be avoided in that although it results in correct logical design of combinational logic circuits,it will actually get the wrong results in the commissioning process.This paper describes a simple method to identify and remove the phenomenon of competition-hazard based on Karnaugh map.

关 键 词：卡诺图 竞争冒险 组合逻辑电路 

分 类 号：TN791[电子电信—电路与系统]