基于SESC仿真器的存储预取器设计  

Memory Prefetcher Design Based on SESC Emulator

作　　者：赵磊[1] 张萌[1] 刘芳[1] 

机构地区：[1]西北工业大学计算机学院,陕西西安710072

出　　处：《计算机与现代化》2013年第6期183-188,共6页Computer and Modernization

基　　金：国家自然科学基金资助项目(60773223;61003037;61173047);教育部博士点基金资助项目(20116102120049);国家863项目(2009AA01Z110)

摘　　要：仿真器是在宿主机上运行并能模拟目标体系结构机器行为的一种软件系统,它可以解释并执行目标体系结构机器上可执行的程序,同时可提供运行时的指令和事件相关记录,以及目标体系结构机器的性能统计参数。系统级体系结构仿真器是可以作为一个虚拟目标机器运行的软件系统,它可以实现对单(多)处理器、内存系统、Cache和外部设备等子系统的功能模拟。本文根据多核处理器结构特点,研究体系结构仿真器与测试程序的设计方法。利用体系结构仿真器,分析不同结构的多核处理器片外存储访问需求,讨论片外存储访问带宽对计算性能的影响问题。总结出多核系统片外存储器访问的机制与需求,以及片外访存与程序特征的关系。The emulator is a software system running on host and simulating the behavior of target architecture machine. It can explain and execute the executable program on target architecture machine, while providing run-time instruction and event-related records, as well as the statistical parameters of target architecture machine performance. System-level architecture emulator can be used as a virtual target machine which running software system, can achieve the functional simulation of the single （multi） processor, system memory, cache, and an external device subsystem. This paper is based on the structural characteristics of multi-core processors, studies architecture simulation and testing procedures. Using architecture simulation, the different structure of multi-core processor chip memory access requirements are analyzed, and the off-chip memory access bandwidth on the impact of computing performance is discussed. The multi-core system-chip memory access mechanism and needs are summed up, as well as off-chip memory access and program characteristics.

关 键 词：体系结构仿真器 SESC 预取器 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]