22-Bit三阶Cascaded结构Sigma-Delta调制器设计  

Design of 22-bit Sigma-Delta modulator with third-order cascaded structure

作　　者：康志宏[1] 李开航[1] 薛佳梅[1] 庄锦清[1] 

机构地区：[1]厦门大学物理与机电工程学院,福建厦门361005

出　　处：《现代电子技术》2013年第12期25-28,共4页Modern Electronics Technique

摘　　要：设计一款可用于称重传感器ADC的高精度2-1级联结构Sigma-Delta调制器。在考虑非理想因素的前提下,采用Matlab/Simulink数学建模和仿真表明,在信号带宽为20 Hz,过采样率为1 024的情况下,该调制器的信噪比为170.7 dB。采用Charter 0.35μm工艺对该调制器进行电路级设计并用Spectre仿真,电路信噪比为144.8 dB,该结果高于22位要求的135 dB。A 22-bit Sigma-Delta modulator with high-accuracy third-order 2-1 cascade structure for weighing sensor ADC is presented in this paper. While the bandwidth of the input signal is 20 Hz and the oversampling ratio is 1024, Matlab/Simu- link mathematical modeling and simulation show that the signal-to-noise ratio （SNR） of the modulator is 170.7 dB in conside- ration of the nonideal factors. The circuit of the modulator is designed with Charter 0.35 Ixm standard CMOS process and simu- lated with Spectre. The result shows that the SNR can reach 144.8 dB, which is higher than 135 dB required by 22-bit Sigma- Delta modulator.

关 键 词：过采样率 SIGMA-DELTA调制器 ADC 电路信噪比 

分 类 号：TN911.34[电子电信—通信与信息系统]