基于VLSI平台的C51处理器仿真与设计  

Simulation and design of C51 processor based on VLSI platform

作　　者：卢莎[1] 何菁[1] 袁杰[2] 

机构地区：[1]南京大学金陵学院,江苏南京210089 [2]南京大学,江苏南京210093

出　　处：《现代电子技术》2013年第12期92-96,共5页Modern Electronics Technique

基　　金：江苏省自然科学基金(BK2010386)

摘　　要：传统ISA处理器内部有限的逻辑资源和外部固定的引脚封装大大的限制了它的应用范围。利用FPGA丰富的逻辑资源实现传统MCU中的各个组成部分,底层采用可配置引脚降低硬件设计复杂度,各模块间采用Wishbone总线结构的方式构建系统,可以达到传统MCU无法完成的要求,具有很好的应用前景。使用硬件描述语言,自底向上设计处理核心80C51,并且与几类通用外设互连组成系统,使用Virtex-ⅡPro系列FPGA进行板级验证。板级验证结果表明实现了既定目标,与标准MCU兼容,系统运行稳定。The internal limited logic resources and external fixed-pin package, which traditional microprocessors are com- posed of, have seriously constrained their ranges of application. Making full use of the abundant logic resources of FPGA can im- plement the various components of the traditional microprocessors. Using the configurable I/O pins can reduce hardware design complexity in bottom layer. Wishbone bus structure is used as a connection between all modules to build a system which can meet the requirements that the standard microprocessors cannot acquired. The system has a good application foreground. The hardware description language is used in this paper to design the bottom-up series of the operating core of $0C51 and connect those cores with some general peripherals to build a minimal system, and run the system in FPGA of ＂Virtex-II Pro series＂ to perform the boards level verification. The result from the boards level verification indicates that the set objective that the system has better compatibility with the standard microprocessors and runs stable.

关 键 词：逻辑资源 VLSI FPGA C51处理器 

分 类 号：TN911.34[电子电信—通信与信息系统] TP368.1[电子电信—信息与通信工程]