基于UVM实现时间同步电路的功能验证  

Function Verification of Time Synchronization Circuit Based on UVM

作　　者：王世中[1] 田泽[1] 吴晓成[1] 张荣华[1] 王治[1] 王纯委[1] 

机构地区：[1]中国航空计算技术研究所,陕西西安710068

出　　处：《计算机技术与发展》2013年第7期183-186,共4页Computer Technology and Development

基　　金："十二五"微电子预研(51308010601);国防预研基金(9140A08010712HK6101);中国航空工业集团公司创新基金(2010BD63111)

摘　　要：时间同步电路模块是某款在研网络通信SoC芯片的核心IP之一,为通信网络子系统之间提供精准的时间同步功能,因此对其功能正确的验证具有重要意义。如果采用传统的定向测试方法对其验证将很难遍历到所有情况,而采用受约束的随机测试、基于覆盖率驱动的UVM验证方法学,能大量减小验证激励的开发项,有效穷举要验证的功能点。文中介绍了基于UVM验证方法学验证平台设计实现的过程,经过仿真验证和覆盖率的统计分析,证明采用该方法能高效地检查出设计的缺陷,减少了验证花费的时间。Time synchronization circuit module that is one important IP core of a developing network communication SoC chip provides precise time synchronization between the communication network subsystems, and therefore their correct functional verification has great significance. Using the traditional directional test method on its validation will be difficult to traverse all cases, and constrained random test,based-coverage driven UVM method, can reduce the test stimulus development, effective exhaustion to verify the function point. In- troduce the verification platform process of design and implementation based on UVM verification methodology, through simulation and the coverage rate of the statistical analysis,prove that the method can effectively check the design defects,reduces verification time.

关 键 词：UVM 覆盖率 寄存器模型 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]