一种用于认知无线电的快速频率合成器设计  

Fast frequency synthesizer design for cognitive radio

作　　者：周斌[1] 曾桂根[1] 

机构地区：[1]南京邮电大学信号处理与传输研究院,江苏南京210003

出　　处：《电子设计工程》2013年第13期184-186,190,共4页Electronic Design Engineering

摘　　要：为了研制一种锁定时间短、相位噪声低、杂散抑制度高的频率合成技术,采用了直接数字式频率合成器(DDS)驱动锁相环(PLL)的结构。该频率合成器综合了DDS频率转换速度快、频率分辨率高和PLL输出频带宽、输出杂散低的优点。基于该结构研制实现了输出频率范围为700～800 MHz的宽带频率合成器,实验结果表明该频率合成器扫描模式Δf=1 MHz锁定时间不超过20μs,跳频模式Δf=50 MHz的定时间不超过30μs,近端杂散抑制度优于-50 dBc。In order to develop a frequency synthesis technology with short locking time,low phase noise and high spurious suppression.The frequency synthesizer used a DDS-driven PLL structure, and it integrated advantages of quick DDS frequency conversion, high frequency resolution,wide PLL output bandwidth and low output spurious. A wideband frequency synthesizer with a 700- 800 MHz frequency output was developed based on this structure, and the experiment results showed that the frequency synthesizer＇s locking time was within 20 μs in scan mode when △f=1MHz, and it＇s locking time was less than 100 μs in hopping mode when △f=50 MHz, proximal spurious rejection was better than -50dBc.

关 键 词：锁定时间 相位噪声 杂散抑制度 直接数字式频率合成器 锁相环 频率合成器 

分 类 号：TN743[电子电信—电路与系统]